1. Field of the Invention
The present invention relates to the field of digital computation and more particularly to sequential logic used to multiply two serial numbers to obtain a serial output, the product being of double precision and reflecting the sign of the operands. The invention is particularly adapted to fabrication using large scale integration.
2. Description of the Prior Art
Multiplication of two binary numbers of m and n bits respectively, if there is no truncation, leads to a product of (m + n) bits, conventionally referred to as a double precision product. When lower accuracy is acceptable, typically comparable to that of the operands, the double precision product is truncated, possibly in formation of the individual partial products. If double precision is sought, that precision must be preserved in the formation of the individual partial products. The double precision product is often required in high precision arithmetic, such as integration.
The present invention represents an outgrowth of earlier work described in U.S. Pat. No. 3,947,670 of John M. Irwin et al, entitled "Signed Multiplication Logic". The patent describes a multiplication logic obtaining a single precision product. The partial product stages described therein form truncated partial products, suitable for formation of a single precision product.